a2retro blog

Uthernet Status - Invector has informed me that they received the new modules but need some time to test them and mount the connectors. I believe the earliest I would be able to ship out new cards will be the end of June. So there is light at the end of the tunnel :o)

SRAM Status - Last update I mentioned I wanted to “get the existing slinky hardware working rock solid on the //c+ so I have a good foundation in which to try and implement the AUX style memory interface.”      I have still not figured this one out and it’s got me stumped, so that’s putting damper on //cmxp progress. :o(

Apple II Emulators - I have spent some time doing some Applewin and kegswin coding. The Applewin update (in code review) is to enable paged EEPROM support for the possibility of a future ROMable version of IP65. The kegswin update adds Uthernet support in slot3 (alpha binary available).

SPI/SDCard status- I haven’t done much with the //c version of this hardware/software since last time but I am designing a 4 port 65SPI/EEPROM(32K) “development” card for the Apple //e in the meantime. This is the hardware equivalent to the software support I have/will code into Applewin.

SPI/SDCard status- I am able to read blocks on both a 32MB and 128MB MMC card. I am also able to read block 0 on a 1GB MicroSD card (have not determined the issue reading other blocks yet). I have not been able to properly init communications to a 4GB MicroSD card. These are what I have on hand to test with at the moment. I have started on a simple RAM resident ProDOS block driver to make it easier to test both reading and writing.

 SRAM Status - I have been considering some feedback given on comp.sys.apple2 to my project. One suggestion from Michael Mahon was to ditch the Slinky emulation and support Ramworks (Z-ram for example) style AUXmem augmentation. This would make it compatible with more software and free up the ROM space of the Slinky driver for use by a SDCard ProDOS block driver.

 I started to investigate how AUX memory works and what might be involved in subverting it in the //c . Since my development platform is the //c+ I also took notice of the additional signals (EN80 and INH) available on the connector located beside the memory expansion port. From what I can tell so far, it may be possible to implement what I want without having to tap the MMU socket directly (at least on a //c+). ROMEN1 Is also available which means I could override the onboard ROM with out having to tap into it. I am still working this out (with the help of Jim Sathers Understanding the Apple //e at my side)

 So the next steps as I see them are to 1) get the existing slinky hardware working rock solid on the //c+ so I have a good foundation in which to try and implement the AUX style memory interface. 2) add support for AUXmem override.

 It may be possible to support both AUXmem and Slinky with the same hardware and a different CPLD code load for each type. (It would also be kind of neat if it could be partitioned for both simultaneously - with a big enough SRAM of course)

• - not started yet //cmxp going to start looking at 65SPI and SDCard circuit next
  
• Started working on this a week or so ago
  
• 
  
• To start with I repurposed a 4×6 perf board that already had a XC9572XL on it that I did my original devsel testing on. That’s it’s main function along with inverting the apple2 read/write signal for the sn74LVCCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER
  
• The SPI logic is a copy of the code from Daryl Rictors 65SPI project. My thanks go out to Daryl for sharing this code with the community and patiently answering all my questions about it.
  
• The code is running in a EZ-DIGITAL XC95144XL-TQ100 breakout board I purchased from Justin.
  
• Murphys law came into effect when I inadvertently set an inversion flag on one of the Logic Analyzer probes which was attached to the MISO line. This stumped me for awhile.
  
• Next up is to write some software to make a loadable disk driver for ProDOS so I can test things out in general. I want to see if the SPI controller runs into the same glitch on the IIc+ as my sram interface did.
  
• Currently wired is a standard SDCard conenctor. I also have a MicroSD card connector wired up for the second SPI device. The third SPI device will be a wifi-card it is surface mountable so I need to make a mini break out for it.
  
• The compact flash interface is mounted but needs to be wire wrapped to the remaining available pins on the CPLD.
  

• Uthernet Status
  • Base Cards have been received. Due to a manufacturing oversight this batch will not have gold fingers.
  • Modules are still delayed from Invector- no ETA at this point.  
     
• Been busy doing a few things in the background (updated) …
  • No progress on the CP2200 driver
  • Got my Applicard remakes from Alex Freed - yay
  • Cypress was kind enough to send me some sram samples, so along with those and the ones I purchased from digi-key I should be able to make a decision. I was also able to get a pair of 512KB NVSRAM’s from cypress so this should make for an interesting test.
    • CYC1049
    • CY62148
    • CY62158 ( I think this is it) 1M x 8
    • Choices for a larger SRAM are
      • CY62167DV30 (2MB)
      • CY62177DV30 (4MB)
      • MT45W8MW16BGXMT (16MB)
    • Putting ram chips on breakouts so I can experiment.
  • Initial protoype will be loaded with several connectors, so I can experiment with the best combination. Here I was just goofing around with possible connector placements. 3×4″ card
     
    • 
    • So this has a CF socket, SDCard socket, MicroSD socket and landing pad for the wireless board, battery holder, cpld, iic bus connector, voltage regulators and a pin out for a ram module. A Production version will have the final ram choice soldered in place and decision will be made CF or SD socket.
  • Reviewing how to add battery backup to the SRAM circuit (no update)
  • Spent some cycles on possible breakout boards to ease further developments
    • Apple 2 Multi-bus breakout board (Applelogic.org org Apple II bus FPGA card got me thinking about this one) - Made some slight progress on this one
      • Similar concept to 8 bit baby but with only Apple Bus connectors on it
        • 50 contact Apple II slot
        • 60 contact Apple II AUX slot
        • 44 contact IIgs Memory slot
        • 34 pin //c memory expansion connector
      • Center area would have room for a Large CPLD XC95144/288XL - probably be a TQ144 to PGA adapter
      • Connectors for daughter piggy back card to hold the downstream circuit. They would have the other mating side of the board connectors on the main board.
      • Updated (slightly) to use FCI BergStak connectors

        

      • All signals are routed from the edge connector to closest board connector. They are also routed (san any power lines) to the closest usable pins on the cpld. Pins from the other side of the cpld are routed to it’s closest board connecter. These signals have possibly had logic applied to them and are for use by the down stream circuit. Since only one bus can be active at a time, having the other busses connect should not affect the downstream circuit.
      • One key thing hear is that it is the daughter module that decides what signals are bridged from the bus to the cpld.
      • Since I have a bunch of XC95288XL chips available to me I might make a second version that has a hardwired CPLD vs the removable one I had planned.  
         
    • Apple 2 EEPROM support on a 32 DIP DIP.
      • I took Rich Dreyer’s EEPROM circuit from the CFFA card and mounted the required chips on a 32 pin DIP format to be used with a breadboard like the Littleproto II
      • This would make it easy to add EPROM support to cards under development.
    • Been refining a PSRAM breakout board for his chip MT45W8MW16BGX
    • Working with a few others on a Apple 2 SDRAM interface (no update)  
       
• Next on the Agenda
  • - not started yet //cmxp going to start looking at 65SPI and SDCard circuit next
  • Got sidetracked on a breakout board for Xilinx XC95288Xl-PQ208 chips as I was able to pickup a bunch on ebay for a really good price. Still needs the by-pass caps added. PCB is 2.2 x 2.2 inches  
     
  • 

     
     

This is a test blog post from OneNote - been organizing my ideas and projects in it. It’s a pretty cool application.

Uthernet Status

• • Base Cards are out in manufacturing
  • Modules are delayed from Invector- no ETA at this point.

Been busy doing a few things in the background …

• • No progress on the CP2200 driver
  • Ordered 2 Applicard remakes from Alex Freed
  • Reorganizing my basement work area
    • Reorganized my desk space and filing areas
    • Put most loose stuff in see through plastic containers
    • Reviewed document Filing system
    • Documenting A2 Card collection
    • Documenting Embedded hardware kits
  • Deciding which SRAM chip to use
    • CYC1049
    • CY62148
    • CY62158 ( I think this is it) 1M x 8
  • Choices for a larger SRAM are
    • CY62167DV30 (2MB)
    • CY62177DV30 (4MB)
    • MT45W8MW16BGXMT (16MB)
  • Reviewing how to add battery backup to the SRAM circuit
  • Spent some cycles on possible breakout boards to ease further developments
    • Apple 2 Multi-bus breakout board (Applelogic.org org Apple II bus FPGA card got me thinking about this one)
      • Similar concept to 8 bit baby but with only Apple Bus connectors on it
        • 50 contact Apple II slot
        • 60 contact Apple II AUX slot
        • 44 contact IIgs Memory slot
        • 34 pin //c memory expansion connector
      • Center area would have room for a Large CPLD XC95144/288XL - probably be a TQ144 to PGA adapter
      • Connectors for daughter piggy back card to hold the downstream circuit. They would have the other mating side of the board connectors on the main board.
      • 
      • All signals are routed from the edge connector to closest board connector. They are also routed (san any power lines) to the closet usable pins on the cpld. Pins from the other side of the cpld are routed toit’s closest board connecter. These signals have possibly had logic applied to them and are for use by the down stream circuit. Since only one bus can be active at a time, having the other busses connect should not affect the downstream circuit.
    • Apple 2 EEPROM support on a 32 DIP DIP.
      • I took Rich Dreyer’s EEPROM circuit from the CFFA card and designed a PCB that mounts the required chips on a 32 pin DIP format to be used with a breadboard like the Littleproto II
      • This would make it easy to add EPROM support to cards under development.
    • Been refining a PSRAM breakout board for this chip MT45W8MW16BGX
    • Working with a few others on a Apple 2 SDRAM interface

• Next on the Agenda
  
  • //cmxp going to start looking at 65SPI and SDCard circuit next

Timing is something that has been frustrating me a lot lately … first with the //cmxp project and now this potential Ethernet card.

The short of it is, I can’t seem to come to grips with the necessary delay required at machine lanuage speeds. Any other method of doing things slowly seems to work and that includes entering the right values in the monitor or single stepping stepping via NoIce. In fact i have written the init program in basic (some peeks and pokes) and even that works fine … grrrr

In trying to port the driver from c over to assembly I’ve come to realize once again how rusty my assembly skills are. So I am doing a combo c/asm dirver just to verify the hardware functionality.

Going to have to shelve things for a bit, probably till after the holidays - too much stuff going on in other areas. If I mange to sneak any time in i’ll post an update ..

Later

All my Uthernet back orders except for one have shipped (Sean I am sorry - we’ll talk) and I am stockless once again. The issue this time is the base cards. I have 12 modules on hand and 50 more on order. I want to make a minor update to carrier and will be submitting an order for more PCB’s real soon now.

On the Ethernet next generation front … I plugged in a new prototype tonight I built a while back. It is based on Silabs CP2200 chip. Some benefits to this chip are that it’s about 30% cheaper then the cs8900a, it has a lot less pins and it’s easier to solder. On the software side not sure from a driver perspective if it will be better or not from a space or performance point of view. For this particular prototype I have chosen to use the non multiplex address method which means most of the registers are directly mapped to the Apples memory in the slot i/o area .. ie c400.c4FF .. The first signs of life are that i can read a few registers and they have the correct power on defaults (although some don’t) and i can change a registers contents and it stays and can be changed back. More info to follow.

Bye

That usually happens with me over the summer .. not much gets done in the hobby space as we are outside enjoying the sunshine … or trying to  … it was quite the rainy summer up in TO this summer.

Uthernet update - I have just received another shipment of modules, so some back orders are going out.   I have been advised that the module I use is being discontinued.  In the short term I plan to stock upon another 50 modules. That should hopefully see me through a decision on what to do next.

The options are

1. Make my own version of the module
2. Redesign the card as an all in one (perhaps add some ROM to it)
3. Replace it with a completely new design (Silabs CP2200 perhaps)

If you have any input I’d like to hear it

Stay tuned …

//cmxp update- When the ball went bouncing down the road back in May, I was stuck on a glitch that still has me scratching my head …. This appears to be random but perhaps my analyser sample isn’t large enough for me to see the big picture.  Something is causing the data-bus to load up with all FF’s prior to it settling down on the vaule i actually want to write and that somehow triggers the address counter to increment prematurely. I have been staring at timing diagrams trying to make sense of it.

Today I recalled that memory cards built for the original //c could not be used in the IIc+ due to a timing problem. I had originally decided to test on the IIc+ so that once i had things down, I figured it should be backward compatible with the original memory expandable //c. On a hunch or perhaps an act of desperation I decided to un-mothball a //c and plugged my memory card into it.  I fired up the diags ($C40AG) and crossed my fingers .. the line of dots kept going and going and going … it made one complete pass .. I let go of my breath then .. I think I was blue  … I kept watching and it didn’t fail … after 10 passes I knew I was out of the woods … so far it has made a total of about 250 passes and no failures yet .. whoopee

Clearly I now have to figure out whats different with the IIc+ from a timing perspective as far as this glitch goes .. at least I know what I have works so far and that’s a step in the right direction. Bring on winter … it’s back to Apple ][ land.

Cheers

To carry on my journey from last time …. I figured out from the Slinky ROM listing, that the diags are expecting to read the values back from the registers used to setup the SRAM addresss. My code to that point was only setup for write access only. So I started to modifiy the code to be able to present this info back to the Apple //c bus. What was odd and continued to drive me nuts over the course of a few weeks was that while the code seemed to work in the simulator and combintorial outputs worked on the real hardware, I could not get the ‘reg’ outputs to drive the sram address lines.

It was getting to the point where I was doubting I had even a basic understanding of what the hell I was doing :) 

I tapped Andre’ LaMothe and Alex Freed for advice but it just would not work. I eventually replaced the CPLD with another one and then it started seeing some signs of life …. after some more experimentation and a few more notes back an forth I have gotten it to work with full read/write of the registers and post increment on the data read/write port. Diags will run but bomb out intermittantly at randow addresses where a 00 is written during one of the tests and a FF is read back. That’s the next thing to track down.

The odd thing is that I can put the the original CPLD back in the circuit and it functions okay… so I am really not sure where I went wrong but it sure gave me an oppertunity to wrack my brain. The logic analyzer was invaluable …. worth every penny.

Well…. the smoke test failed …. I could smell burning somethng ….. turns out I made a  very big mistake … when looking at the memory expansion connector in the IIc memory technical reference and the IIc technical reference, I thought the pinout was as if you were looking down on the the connector in the machine … what they are actually showing is the memory connector on the card facing up … needless to say I had every thing ass backwards … rather then go an rip every thing apart I have used some lead cables and a IDC 34 connector to fix things up for now …

So once I got the system booting again, I was able to successfully program the XC95108 with the jed file I programmed. Next I tried executing the diag code for the memory card @ c40a … it failed with an address error … so thats where I will start my investigations .. I will put the logic analyzer on the Apple side to start to make sure the CPLD is getting all the signals properly … then once I have determined that I will put the probes on the sram side to make sure the ram is reacting properly.