Doing another run of Uthernet cards. Also working on a project in the background revolving around another attempt at getting WiFi running on an Apple II.
Archive for the ‘Uncategorized’ Category
As part of my memory investigation I purchased these two products (there is a SDCard adapter beside them for comparison purposes)
- M6MGT321s4TP - Flash + SRAM ( 512K+512K?)
- XILINX Spartan XCS50A - VQG100AGQ1041
- MicroSD slot
(Sorry the pics are a little blurry. Also notice the cartridge fingers are already corroded and need to be cleaned up a little).
To mount this cart on a test PCB i’ll be looking to pick up one of these
- Altera MAX II EPM240T100I5N
- Fujitsu - 84VZ046G-60 (32MB Flash + 512K SRAM - Battery backed)
- Fujitsu - 84VZ128D-70 (16MB PSRAM)
Uthernet Status - Invector has informed me that they received the new modules but need some time to test them and mount the connectors. I believe the earliest I would be able to ship out new cards will be the end of June. So there is light at the end of the tunnel :o)
SRAM Status - Last update I mentioned I wanted to “get the existing slinky hardware working rock solid on the //c+ so I have a good foundation in which to try and implement the AUX style memory interface.” I have still not figured this one out and it’s got me stumped, so that’s putting damper on //cmxp progress. :o(
Apple II Emulators - I have spent some time doing some Applewin and kegswin coding. The Applewin update (in code review) is to enable paged EEPROM support for the possibility of a future ROMable version of IP65. The kegswin update adds Uthernet support in slot3 (alpha binary available).
SPI/SDCard status- I haven’t done much with the //c version of this hardware/software since last time but I am designing a 4 port 65SPI/EEPROM(32K) “development” card for the Apple //e in the meantime. This is the hardware equivalent to the software support I have/will code into Applewin.
- Base Cards have been received. Due to a manufacturing oversight this batch will not have gold fingers.
- Modules are still delayed from Invector- no ETA at this point.
Been busy doing a few things in the background (updated) …
- No progress on the CP2200 driver
- Got my Applicard remakes from Alex Freed - yay
Cypress was kind enough to send me some sram samples, so along with those and the ones I purchased from digi-key I should be able to make a decision. I was also able to get a pair of 512KB NVSRAM’s from cypress so this should make for an interesting test.
- CY62158 ( I think this is it) 1M x 8
Choices for a larger SRAM are
- CY62167DV30 (2MB)
- CY62177DV30 (4MB)
- MT45W8MW16BGXMT (16MB)
- Putting ram chips on breakouts so I can experiment.
Initial protoype will be loaded with several connectors, so I can experiment with the best combination. Here I was just goofing around with possible connector placements. 3×4″ card
So this has a CF socket, SDCard socket, MicroSD socket and landing pad for the wireless board, battery holder, cpld, iic bus connector, voltage regulators and a pin out for a ram module. A Production version will have the final ram choice soldered in place and decision will be made CF or SD socket.
- Reviewing how to add battery backup to the SRAM circuit (no update)
Spent some cycles on possible breakout boards to ease further developments
Apple 2 Multi-bus breakout board (Applelogic.org org Apple II bus FPGA card got me thinking about this one) - Made some slight progress on this one
Similar concept to 8 bit baby but with only Apple Bus connectors on it
- 50 contact Apple II slot
- 60 contact Apple II AUX slot
- 44 contact IIgs Memory slot
- 34 pin //c memory expansion connector
- Center area would have room for a Large CPLD XC95144/288XL - probably be a TQ144 to PGA adapter
- Connectors for daughter piggy back card to hold the downstream circuit. They would have the other mating side of the board connectors on the main board.
Updated (slightly) to use FCI BergStak connectors
- All signals are routed from the edge connector to closest board connector. They are also routed (san any power lines) to the closest usable pins on the cpld. Pins from the other side of the cpld are routed to it’s closest board connecter. These signals have possibly had logic applied to them and are for use by the down stream circuit. Since only one bus can be active at a time, having the other busses connect should not affect the downstream circuit.
- One key thing hear is that it is the daughter module that decides what signals are bridged from the bus to the cpld.
Since I have a bunch of XC95288XL chips available to me I might make a second version that has a hardwired CPLD vs the removable one I had planned.
Apple 2 EEPROM support on a 32 DIP DIP.
- I took Rich Dreyer’s EEPROM circuit from the CFFA card and mounted the required chips on a 32 pin DIP format to be used with a breadboard like the Littleproto II
- This would make it easy to add EPROM support to cards under development.
- Been refining a PSRAM breakout board for his chip MT45W8MW16BGX
Working with a few others on a Apple 2 SDRAM interface (no update)
Next on the Agenda
- - not started yet //cmxp going to start looking at 65SPI and SDCard circuit next
Got sidetracked on a breakout board for Xilinx XC95288Xl-PQ208 chips as I was able to pickup a bunch on ebay for a really good price. Still needs the by-pass caps added. PCB is 2.2 x 2.2 inches
All the Uthernets are now out the door now … so hopefully I can get back to working on IIcmxp …