Archive for the ‘//cmxp’ Category

New hardware starts to roll in … Part 1

Monday, February 21st, 2011

I have been on a bit of a spending spree lately … I thought I would share what I have been buying as it comes in and then work it into my development plans.

My first items were some prototyping supplies from a place called – Proto Advantage

http://www.proto-advantage.com

They have a good selection of stuff and prices are pretty reasonable

Products

——————————————————

Vacuum Pen (TLVACPEN)
Premium Jumper Wires 6″ M/M Pack of 10 (WRMM10)
Premium Jumper Wires 6″ F/F Pack of 10 (WRFF10)
Magnifier 10x – Illuminated With High Power White LEDs (TLMAG01)
Deluxe Test Lead Set (TL-22)
Banana to Minigrabber Set (TL-12)
Solder Paste 0.5cc 63/37 Sn/Pb No Clean (SLD005CC-NC-PB)
Solder Paste Dispensing Needle Kit – 11 piece (DISPNDLEKIT1)
ESD Electronics Tweezers (TWESD-15)
TSOP-54 (II) (0.8 mm pitch, 10.16 mm body) PCB and Stencil Kit (PA0210-KIT)
PQFP-208 (0.5 mm pitch, 28 x 28 mm body) PCB and Stencil Kit (PA0202-KIT)

So you can probably tell from some of those items that I want to start experimenting with doing my own surface mount components for prototyping.

The second batch of items to arrive were some AVR XMega128 dev boards I recently acquired from ALVIDI.

The ones I picked up were the AL-XAVRB V2.0

These are nice boards at a very reasonable price – approx $45. Looking forward to see how I can integrate these into some of my co-processor based designs.

128K Flash, 8K SRAM, 2K EPROM, MicroSD socket and 16 or 32MB SDRAM

Still working on my follow up posts about RAM, STORAGE and NETWORK

Tik Tok, another year rolls by the clock …

Thursday, February 17th, 2011

I still get notifications from A2central, which I always read even though I was pretty much trying to tune everything else “Apple II related” out (except for shipping Uthernet’s in the pipeline).

If I may digress for a moment … for me it’s kind of like quitting smoking … very hard to go cold turkey but doable … then if you sucum to temptation and think I’ll just have just one or two … boom … your sucked right back into the vortex … (I still am cigarette free after 29 years but okay I’ll admit i have the odd Colt once in a awhile with a beer).  I don’t think i’ll ever quite be, 100% over,  I’d like to have a smoke feeling .

So now your wondering what’s this got to do with Apple II’s? Read on  …

On January 28th 2011, Sean posted a pointer to Robert Justice’s Apple IIc Smartport device posting on CSA2 … that was the thing that pulled me back into the vortex from my self induced “no Apple II tinkering” coma. If you’ve been reading my blog all along or read through my forums you know this a project I wanted to do. I had acquired a Chinook Ct-20c to reverse engineer it but got side tracked onto other projects. I am glad Robert finally figured it out. Way to go Robert!!

Re-creating Roberts project with my XGS AVR 8 development system using a MicroSD card was very straight forward. In fact getting the ascii terminal for debugging output gave me the most grief. Reading worked right way but I had to step the SPI clock down quite a bit in order for the write function to work properly. As it stand now, it works well in a IIc (no pass through support yet) and in a IIc+ works fine for the most part but still has an issue with the internal drive where it cannot be used after the external dirve has been initialized.  Haven’t been able to puzzle that one out yet.

:) So now it’s nice to be back if only part time ..

I spent the last few days reacquainting myself with some of the projects I was working on and look forward to actually completing some of this stuff.  I plan on resurrecting the IIcxmp project If anyone out there is still reading this blog and if you have any skills to help me debug this Apple IIc+ bus problem I would love to hear from you.

The IIcmxp is meant to be an internal option that centers around a memory upgrade, mass storage and networking. I had a 1MB SRAM based memory replacement in beta mode, working well in a IIc but still with bus issues in a IIc+. I had a SPI/SDcard interface (based on Daryl Rictors SPI code) in alpha mode reading SDCards. I had also purchased zero G wifi modules but not got the module hooked up or code ported from PIC/AVR land to 6502.

To get my feet wet again I plan step back and get the sub-components working in a regular Apple IIe/IIgs first before i reintegrate them for the IIcmxp.

That’s the basic plan .. I will follow up with three more posts, one for each section, where I see my journey going and what I will be looking at to get from point A to point B for each component.

So if your still following along … stay tuned …

May 21st Update

Friday, May 22nd, 2009

Uthernet Status – Invector has informed me that they received the new modules but need some time to test them and mount the connectors. I believe the earliest I would be able to ship out new cards will be the end of June. So there is light at the end of the tunnel :o)

SRAM Status – Last update I mentioned I wanted to “get the existing slinky hardware working rock solid on the //c+ so I have a good foundation in which to try and implement the AUX style memory interface.”      I have still not figured this one out and it’s got me stumped, so that’s putting damper on //cmxp progress. :o(

Apple II Emulators – I have spent some time doing some Applewin and kegswin coding. The Applewin update (in code review) is to enable paged EEPROM support for the possibility of a future ROMable version of IP65. The kegswin update adds Uthernet support in slot3 (alpha binary available).

SPI/SDCard status- I haven’t done much with the //c version of this hardware/software since last time but I am designing a 4 port 65SPI/EEPROM(32K) “development” card for the Apple //e in the meantime. This is the hardware equivalent to the software support I have/will code into Applewin.


April 28th Update – Back to drawing board. :o)

Tuesday, April 28th, 2009

SPI/SDCard status- I am able to read blocks on both a 32MB and 128MB MMC card. I am also able to read block 0 on a 1GB MicroSD card (have not determined the issue reading other blocks yet). I have not been able to properly init communications to a 4GB MicroSD card. These are what I have on hand to test with at the moment. I have started on a simple RAM resident ProDOS block driver to make it easier to test both reading and writing.

 SRAM Status – I have been considering some feedback given on comp.sys.apple2 to my project. One suggestion from Michael Mahon was to ditch the Slinky emulation and support Ramworks (Z-ram for example) style AUXmem augmentation. This would make it compatible with more software and free up the ROM space of the Slinky driver for use by a SDCard ProDOS block driver.

 I started to investigate how AUX memory works and what might be involved in subverting it in the //c . Since my development platform is the //c+ I also took notice of the additional signals (EN80 and INH) available on the connector located beside the memory expansion port. From what I can tell so far, it may be possible to implement what I want without having to tap the MMU socket directly (at least on a //c+). ROMEN1 Is also available which means I could override the onboard ROM with out having to tap into it. I am still working this out (with the help of Jim Sathers Understanding the Apple //e at my side)

 So the next steps as I see them are to 1) get the existing slinky hardware working rock solid on the //c+ so I have a good foundation in which to try and implement the AUX style memory interface. 2) add support for AUXmem override.

 It may be possible to support both AUXmem and Slinky with the same hardware and a different CPLD code load for each type. (It would also be kind of neat if it could be partitioned for both simultaneously – with a big enough SRAM of course)

Apr 19th Update

Sunday, April 19th, 2009
  • :( – not started yet //cmxp going to start looking at 65SPI and SDCard circuit next
  • Started working on this a week or so ago

  • To start with I repurposed a 4×6 perf board that already had a XC9572XL on it that I did my original devsel testing on. That’s it’s main function along with inverting the apple2 read/write signal for the sn74LVCCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER
  • The SPI logic is a copy of the code from Daryl Rictors 65SPI project. My thanks go out to Daryl for sharing this code with the community and patiently answering all my questions about it.
  • The code is running in a EZ-DIGITAL XC95144XL-TQ100 breakout board I purchased from Justin.
  • Murphys law came into effect when I inadvertently set an inversion flag on one of the Logic Analyzer probes which was attached to the MISO line. This stumped me for awhile.
  • Next up is to write some software to make a loadable disk driver for ProDOS so I can test things out in general. I want to see if the SPI controller runs into the same glitch on the IIc+ as my sram interface did.
  • Currently wired is a standard SDCard conenctor. I also have a MicroSD card connector wired up for the second SPI device. The third SPI device will be a wifi-card it is surface mountable so I need to make a mini break out for it.
  • The compact flash interface is mounted but needs to be wire wrapped to the remaining available pins on the CPLD.

Posting from OneNote

Sunday, February 15th, 2009

This is a test blog post from OneNote – been organizing my ideas and projects in it. It’s a pretty cool application.

Uthernet Status

    • Base Cards are out in manufacturing
    • Modules are delayed from Invector- no ETA at this point.

Been busy doing a few things in the background …

    • No progress on the CP2200 driver
    • Ordered 2 Applicard remakes from Alex Freed
    • Reorganizing my basement work area
      • Reorganized my desk space and filing areas
      • Put most loose stuff in see through plastic containers
      • Reviewed document Filing system
      • Documenting A2 Card collection
      • Documenting Embedded hardware kits
    • Deciding which SRAM chip to use
      • CYC1049
      • CY62148
      • CY62158 ( I think this is it) 1M x 8
    • Choices for a larger SRAM are
      • CY62167DV30 (2MB)
      • CY62177DV30 (4MB)
      • MT45W8MW16BGXMT (16MB)
    • Reviewing how to add battery backup to the SRAM circuit
    • Spent some cycles on possible breakout boards to ease further developments
      • Apple 2 Multi-bus breakout board (Applelogic.org org Apple II bus FPGA card got me thinking about this one)
        • Similar concept to 8 bit baby but with only Apple Bus connectors on it
          • 50 contact Apple II slot
          • 60 contact Apple II AUX slot
          • 44 contact IIgs Memory slot
          • 34 pin //c memory expansion connector
        • Center area would have room for a Large CPLD XC95144/288XL – probably be a TQ144 to PGA adapter
        • Connectors for daughter piggy back card to hold the downstream circuit. They would have the other mating side of the board connectors on the main board.
        • All signals are routed from the edge connector to closest board connector. They are also routed (san any power lines) to the closet usable pins on the cpld. Pins from the other side of the cpld are routed toit’s closest board connecter. These signals have possibly had logic applied to them and are for use by the down stream circuit. Since only one bus can be active at a time, having the other busses connect should not affect the downstream circuit.
      • Apple 2 EEPROM support on a 32 DIP DIP.
        • I took Rich Dreyer’s EEPROM circuit from the CFFA card and designed a PCB that mounts the required chips on a 32 pin DIP format to be used with a breadboard like the Littleproto II
        • This would make it easy to add EPROM support to cards under development.
      • Been refining a PSRAM breakout board for this chip MT45W8MW16BGX
      • Working with a few others on a Apple 2 SDRAM interface

  • Next on the Agenda
    • //cmxp going to start looking at 65SPI and SDCard circuit next

Dropping the ball

Thursday, November 6th, 2008

That usually happens with me over the summer .. not much gets done in the hobby space as we are outside enjoying the sunshine … or trying to  … it was quite the rainy summer up in TO this summer.

Uthernet update – I have just received another shipment of modules, so some back orders are going out.   I have been advised that the module I use is being discontinued.  In the short term I plan to stock upon another 50 modules. That should hopefully see me through a decision on what to do next.

The options are

  1. Make my own version of the module
  2. Redesign the card as an all in one (perhaps add some ROM to it)
  3. Replace it with a completely new design (Silabs CP2200 perhaps)

If you have any input I’d like to hear it

Stay tuned …

//cmxp update- When the ball went bouncing down the road back in May, I was stuck on a glitch that still has me scratching my head …. This appears to be random but perhaps my analyser sample isn’t large enough for me to see the big picture.  Something is causing the data-bus to load up with all FF’s prior to it settling down on the vaule i actually want to write and that somehow triggers the address counter to increment prematurely. I have been staring at timing diagrams trying to make sense of it.

Today I recalled that memory cards built for the original //c could not be used in the IIc+ due to a timing problem. I had originally decided to test on the IIc+ so that once i had things down, I figured it should be backward compatible with the original memory expandable //c. On a hunch or perhaps an act of desperation I decided to un-mothball a //c and plugged my memory card into it.  I fired up the diags ($C40AG) and crossed my fingers .. the line of dots kept going and going and going … it made one complete pass .. I let go of my breath then .. I think I was blue  … I kept watching and it didn’t fail … after 10 passes I knew I was out of the woods … so far it has made a total of about 250 passes and no failures yet .. whoopee

Clearly I now have to figure out whats different with the IIc+ from a timing perspective as far as this glitch goes .. at least I know what I have works so far and that’s a step in the right direction. Bring on winter … it’s back to Apple ][ land.

Cheers

Helluva Ride (and it’s not over yet)

Friday, May 30th, 2008

To carry on my journey from last time …. I figured out from the Slinky ROM listing, that the diags are expecting to read the values back from the registers used to setup the SRAM addresss. My code to that point was only setup for write access only. So I started to modifiy the code to be able to present this info back to the Apple //c bus. What was odd and continued to drive me nuts over the course of a few weeks was that while the code seemed to work in the simulator and combintorial outputs worked on the real hardware, I could not get the ‘reg’ outputs to drive the sram address lines.

It was getting to the point where I was doubting I had even a basic understanding of what the hell I was doing :) 

I tapped Andre’ LaMothe and Alex Freed for advice but it just would not work. I eventually replaced the CPLD with another one and then it started seeing some signs of life …. after some more experimentation and a few more notes back an forth I have gotten it to work with full read/write of the registers and post increment on the data read/write port. Diags will run but bomb out intermittantly at randow addresses where a 00 is written during one of the tests and a FF is read back. That’s the next thing to track down.

The odd thing is that I can put the the original CPLD back in the circuit and it functions okay… so I am really not sure where I went wrong but it sure gave me an oppertunity to wrack my brain. The logic analyzer was invaluable …. worth every penny.

Smoke Test …

Tuesday, May 6th, 2008

Well…. the smoke test failed …. I could smell burning somethng ….. turns out I made a  very big mistake … when looking at the memory expansion connector in the IIc memory technical reference and the IIc technical reference, I thought the pinout was as if you were looking down on the the connector in the machine … what they are actually showing is the memory connector on the card facing up … needless to say I had every thing ass backwards … rather then go an rip every thing apart I have used some lead cables and a IDC 34 connector to fix things up for now …

So once I got the system booting again, I was able to successfully program the XC95108 with the jed file I programmed. Next I tried executing the diag code for the memory card @ c40a … it failed with an address error … so thats where I will start my investigations .. I will put the logic analyzer on the Apple side to start to make sure the CPLD is getting all the signals properly … then once I have determined that I will put the probes on the sram side to make sure the ram is reacting properly.

Uthernet cards available for sale again

Wednesday, April 9th, 2008

I have 3 prepaid orders to fill and then a supply of 28 cards available for sale. Anyone on my interrested parties list should have gotten a note from me.

Also I am half finished wiring up the 5v SRAM interface for the IIc. Hope to try that out in a few days.

Sram

If anyone knows of a PCB assembly house that will do microBGA or CP scale packages for a reasonable price then please drop me a line.