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Archive for the 'Uthernet II' Category

Uthernet II Update – Part 3

Friday, May 29th, 2015

Finished Product

New boards are in hand and all the parts and stencil as well. I did a build last night and so far on my test IIe the web page loading test has almost been running for 11 hours without any failures. So at least at this point there are no regressions.

 

View the results of preliminary testing the first card here

 

Finished Product

Uthernet II update

Monday, March 30th, 2015

Sorry folks … been a long time coming but an update is finally here.

About a year ago I was sending out first alpha, then beta versions of the new Uthernet II card. As I had done most of my testing in a IIgs Rom1 and an enhanced IIe, I was dismayed to find out that the card was not working properly in a unenhanced IIe or in most IIgs ROM3’s.There were two issues 1) the timing was off and there were intermittent problems and the interrupt line caused issues in the IIgs with the control panel activation sequence.

With Kilian Leonhardt and Daniel Krue’s suggestions I was able to update the circuit so that both of these problems are no longer an issue based on the testing both Kilian and I have done. So I made modifications to the PCB and just today received some new boards. Later this week I will be cooking up a few and then will proceed with the final testing.

PCB_rev3

 

After that if all goes well, I plan to send out a small survey with a few questions and then we can proceed with taking pre-orders.