Doing another run of Uthernet cards. Also working on a project in the background revolving around another attempt at getting WiFi running on an Apple II.
Disclaimer: I am trying to be technically accurate but please send any comments or corrections and I will update this blog post.
This blog entry is going to be about RAM. There are 5 main types I am going to cover and discuss their applicability to some of the projects I am working on.
We have two families of RAM – Dynamic RAM (DRAM and SDRAM) and Static RAM (SRAM, NVRAM, PSRAM).
When the Apple II was in it’s heyday, DRAM was popular because it was cheaper then most other types of memory. There were a few memory cards made with SRAM later in the cycle but the predominant memory used inside the Apple and on expansion cards was DRAM. It came in various bit configurations 1x64Kbits, 1x256Kbits 1x1024Kbits, 4x64Kbits etc … eventually chips were mounted on a simm vs being socketed or directly soldered. One of the side effects of DRAM’s are they have to be constantly refreshed and that was accomplished on the Apple II during the video display cycle (read Jim Sathers – Understanding the Apple II or Iie for the best technical description of how this works). DRAM also worked with a multiplexed address bus where usually the row addresses was applied followed by the column address to get the final bit location in a chip
When SyncronousDRAM (SDRAM) started appearing, the simm/dimm started having BGA (ball grid array) chips mounted on the simm’s vs DIP or other SMT form factors. While SDRAM’s are more complicated to design in a system because they require a synchronized clock signal and they need to be initialized before they can be used after power up, they also have the benefit of having much higher bit densities then previous DRAM’s. Single chips can have 64, 128 and 256M bits and being DRAM they still need to be refreshed although some SDRAM have auto refresh circuitry built in.
SRAM started to be come more prevalent in the late? 80’s. The Applied Engineering Pocket Rocket was one example of a static ram based RAM card. Static rams come in various bit densities today, you can get 4, 8 and even 16Mbit single chips. These are nowhere near the densities of SDRAM and quite a bit more expensive. Some additional benefits of SRAM are that you can find high speed SRAMS typically used for cache or you can find low power srams used in embedded systems. In fact most microcontrollers today come with some amount of internal SRAM. SRAM can be battery backed in order to retain it’s bits or you could employ a specific type of SRAM called NVRAM which is in most cases a SRAM with a battery in a single package. Cypress does make an actual NVSRAM chip that uses something called QuantumTrap cell vs a battery but these along with NVRAM are expen$ive.
PSRAM‘s (Pseudo Static Ram) are kind if like the best of both worlds. It is typically SDRAM memory packaged with a SRAM like interface (non multiplexed address lines) and auto refresh circuitry. You get the benefit of simple SRAM interface, higher bit densities (128Mbits) and typically lower power consumption. These chips were designed for cell phones (it’s called Cellular RAM by some companies) and only comes in VFBGA (very fine BGA) packages which make it hard to use in prototypes or small runs. It is more expensive then SDRAM but significantly cheaper when compared to regular SRAM in terms of actual chip cost and PCB board space.
Projects that need RAM
My IIcmxp project for the IIc started out as a mass storage solution for the memory expandable Iic and above but it quickly became apparent to me that folks might not want to toss out a perfectly good 1MB ram card in order to replace it with a mass storage solution. So I started working on a 1MB SRAM add-on for the IIcxmp. If you want more details about that project (and where it stalled) read some of my older blog posts.
While I have implemented SRAM, I have also been wanting to see if some of these other types of RAM could be applied to this and other projects.
So as a sub/side project I am working on a 16MB slinky project. Why slinky vs AUX style memory you say … well I would like my research to be applicable to that style or Iigs Ram cards as well but Slinky is the simplest to implement as a test fixture, using different memory modules. Once these various modules are tested and understood then work on using them can begin to be applied to these other designs. Possible uses could be Ram expansion for existing Ramworks and Ramfactor cards or complete replacements for Iigs memory cards, Ramworks, Ramfactor, Slinky etc,
Slinky Base card (test fixture)
The base card consists of a XC95144XL CPLD, 74LVCC4245 transceiver and a 8KB EEPROM. The CPLD and 245 are 3.3v devices but are 5v tolerant. I am still waffling on using a 5v vs a 3.3v EEPROM (I was hoping to use my wilem EPROM programmer vs doing it in system but we’ll see).
I plan on testing 4 memory modules.
Basic SDRAM: First one is a 32MB SDRAM memory module originally developed for Parallax Propeller based systems. You can find a link here. I ordered this module a few weeks ago. Still waiting for it to arrive. I expect the CPLD to be setup to do the initial configuration and linear to R/C address conversion.
XAVR Coprocessor: Second one is the nice module I mentioned earlier which can be the basis for any number of projects. This time around it will mainly be used to serve up RAM from the SDRAM module. Might possibly be considered a prototyping option for the Iicmxp as well.
XRAM: The 3rd option is a multichip smorgasbord of Cypress RAM totaling 4MB. This module will let me test various SRAM modules a) CY14B104L NVSRAM – 512K (will use 2 for a total of 1MB), b) CY62158EV30LL – SRAM 1MB and c) CY62167DV30LL – SRAM 2MB
EZFlash 3n1: I plan to investigate the possibility of repurposing of this module to access the 16MB of PSRAM and possibly the 512K of battery backed SRAM. If this module was used on a Iigs memory card it’s possible? it could be configured to provide 8MB RAM and 8MB of ROM(Flash).
The basic SDRAM module is already pre-built but the others I am going to have to bring to life on some prototyping board.
1) Receive a few more breakout boards kits for TSOP I and II devices.
2) Received my Sparkfun order which consisted of a
Two bluetooth modules for a non apple II related Lego NXT project
SPI based clock calendar chip to develop a SPI module for my 4 Port SPI card – AppleSPI.
As part of my memory investigation I purchased these two products (there is a SDCard adapter beside them for comparison purposes)
- M6MGT321s4TP – Flash + SRAM ( 512K+512K?)
- XILINX Spartan XCS50A – VQG100AGQ1041
- MicroSD slot
(Sorry the pics are a little blurry. Also notice the cartridge fingers are already corroded and need to be cleaned up a little).
To mount this cart on a test PCB i’ll be looking to pick up one of these
- Altera MAX II EPM240T100I5N
- Fujitsu – 84VZ046G-60 (32MB Flash + 512K SRAM – Battery backed)
- Fujitsu – 84VZ128D-70 (16MB PSRAM)
I have been on a bit of a spending spree lately … I thought I would share what I have been buying as it comes in and then work it into my development plans.
My first items were some prototyping supplies from a place called – Proto Advantage
They have a good selection of stuff and prices are pretty reasonable
Vacuum Pen (TLVACPEN)
Premium Jumper Wires 6″ M/M Pack of 10 (WRMM10)
Premium Jumper Wires 6″ F/F Pack of 10 (WRFF10)
Magnifier 10x – Illuminated With High Power White LEDs (TLMAG01)
Deluxe Test Lead Set (TL-22)
Banana to Minigrabber Set (TL-12)
Solder Paste 0.5cc 63/37 Sn/Pb No Clean (SLD005CC-NC-PB)
Solder Paste Dispensing Needle Kit – 11 piece (DISPNDLEKIT1)
ESD Electronics Tweezers (TWESD-15)
TSOP-54 (II) (0.8 mm pitch, 10.16 mm body) PCB and Stencil Kit (PA0210-KIT)
PQFP-208 (0.5 mm pitch, 28 x 28 mm body) PCB and Stencil Kit (PA0202-KIT)
So you can probably tell from some of those items that I want to start experimenting with doing my own surface mount components for prototyping.
The second batch of items to arrive were some AVR XMega128 dev boards I recently acquired from ALVIDI.
The ones I picked up were the AL-XAVRB V2.0
These are nice boards at a very reasonable price – approx $45. Looking forward to see how I can integrate these into some of my co-processor based designs.
128K Flash, 8K SRAM, 2K EPROM, MicroSD socket and 16 or 32MB SDRAM
Still working on my follow up posts about RAM, STORAGE and NETWORK
I still get notifications from A2central, which I always read even though I was pretty much trying to tune everything else “Apple II related” out (except for shipping Uthernet’s in the pipeline).
If I may digress for a moment … for me it’s kind of like quitting smoking … very hard to go cold turkey but doable … then if you sucum to temptation and think I’ll just have just one or two … boom … your sucked right back into the vortex … (I still am cigarette free after 29 years but okay I’ll admit i have the odd Colt once in a awhile with a beer). I don’t think i’ll ever quite be, 100% over, I’d like to have a smoke feeling .
So now your wondering what’s this got to do with Apple II’s? Read on …
On January 28th 2011, Sean posted a pointer to Robert Justice’s Apple IIc Smartport device posting on CSA2 … that was the thing that pulled me back into the vortex from my self induced “no Apple II tinkering” coma. If you’ve been reading my blog all along or read through my forums you know this a project I wanted to do. I had acquired a Chinook Ct-20c to reverse engineer it but got side tracked onto other projects. I am glad Robert finally figured it out. Way to go Robert!!
Re-creating Roberts project with my XGS AVR 8 development system using a MicroSD card was very straight forward. In fact getting the ascii terminal for debugging output gave me the most grief. Reading worked right way but I had to step the SPI clock down quite a bit in order for the write function to work properly. As it stand now, it works well in a IIc (no pass through support yet) and in a IIc+ works fine for the most part but still has an issue with the internal drive where it cannot be used after the external dirve has been initialized. Haven’t been able to puzzle that one out yet.
So now it’s nice to be back if only part time ..
I spent the last few days reacquainting myself with some of the projects I was working on and look forward to actually completing some of this stuff. I plan on resurrecting the IIcxmp project If anyone out there is still reading this blog and if you have any skills to help me debug this Apple IIc+ bus problem I would love to hear from you.
The IIcmxp is meant to be an internal option that centers around a memory upgrade, mass storage and networking. I had a 1MB SRAM based memory replacement in beta mode, working well in a IIc but still with bus issues in a IIc+. I had a SPI/SDcard interface (based on Daryl Rictors SPI code) in alpha mode reading SDCards. I had also purchased zero G wifi modules but not got the module hooked up or code ported from PIC/AVR land to 6502.
To get my feet wet again I plan step back and get the sub-components working in a regular Apple IIe/IIgs first before i reintegrate them for the IIcmxp.
That’s the basic plan .. I will follow up with three more posts, one for each section, where I see my journey going and what I will be looking at to get from point A to point B for each component.
So if your still following along … stay tuned …
Well most everything has been on hold but not forgotten. Other things have had to come first. So any Apple II tinkering has primarily been on the “thought” end vs the soldering iron.
I am still putting out batchs of Uthernets when I can.
I have recently joined the GSport initiative and plan to merge some Applewin changes I was working on last year back in.
Thats about it for now.
I hope your Apple II endeavors are going better then mine.
Uthernet Status – Invector has informed me that they received the new modules but need some time to test them and mount the connectors. I believe the earliest I would be able to ship out new cards will be the end of June. So there is light at the end of the tunnel :o)
SRAM Status – Last update I mentioned I wanted to “get the existing slinky hardware working rock solid on the //c+ so I have a good foundation in which to try and implement the AUX style memory interface.” I have still not figured this one out and it’s got me stumped, so that’s putting damper on //cmxp progress. :o(
Apple II Emulators – I have spent some time doing some Applewin and kegswin coding. The Applewin update (in code review) is to enable paged EEPROM support for the possibility of a future ROMable version of IP65. The kegswin update adds Uthernet support in slot3 (alpha binary available).
SPI/SDCard status– I haven’t done much with the //c version of this hardware/software since last time but I am designing a 4 port 65SPI/EEPROM(32K) “development” card for the Apple //e in the meantime. This is the hardware equivalent to the software support I have/will code into Applewin.
SPI/SDCard status– I am able to read blocks on both a 32MB and 128MB MMC card. I am also able to read block 0 on a 1GB MicroSD card (have not determined the issue reading other blocks yet). I have not been able to properly init communications to a 4GB MicroSD card. These are what I have on hand to test with at the moment. I have started on a simple RAM resident ProDOS block driver to make it easier to test both reading and writing.
SRAM Status – I have been considering some feedback given on comp.sys.apple2 to my project. One suggestion from Michael Mahon was to ditch the Slinky emulation and support Ramworks (Z-ram for example) style AUXmem augmentation. This would make it compatible with more software and free up the ROM space of the Slinky driver for use by a SDCard ProDOS block driver.
I started to investigate how AUX memory works and what might be involved in subverting it in the //c . Since my development platform is the //c+ I also took notice of the additional signals (EN80 and INH) available on the connector located beside the memory expansion port. From what I can tell so far, it may be possible to implement what I want without having to tap the MMU socket directly (at least on a //c+). ROMEN1 Is also available which means I could override the onboard ROM with out having to tap into it. I am still working this out (with the help of Jim Sathers Understanding the Apple //e at my side)
So the next steps as I see them are to 1) get the existing slinky hardware working rock solid on the //c+ so I have a good foundation in which to try and implement the AUX style memory interface. 2) add support for AUXmem override.
It may be possible to support both AUXmem and Slinky with the same hardware and a different CPLD code load for each type. (It would also be kind of neat if it could be partitioned for both simultaneously – with a big enough SRAM of course)
- – not started yet //cmxp going to start looking at 65SPI and SDCard circuit next
- Started working on this a week or so ago
- To start with I repurposed a 4×6 perf board that already had a XC9572XL on it that I did my original devsel testing on. That’s it’s main function along with inverting the apple2 read/write signal for the sn74LVCCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER
- The SPI logic is a copy of the code from Daryl Rictors 65SPI project. My thanks go out to Daryl for sharing this code with the community and patiently answering all my questions about it.
- The code is running in a EZ-DIGITAL XC95144XL-TQ100 breakout board I purchased from Justin.
- Murphys law came into effect when I inadvertently set an inversion flag on one of the Logic Analyzer probes which was attached to the MISO line. This stumped me for awhile.
- Next up is to write some software to make a loadable disk driver for ProDOS so I can test things out in general. I want to see if the SPI controller runs into the same glitch on the IIc+ as my sram interface did.
- Currently wired is a standard SDCard conenctor. I also have a MicroSD card connector wired up for the second SPI device. The third SPI device will be a wifi-card it is surface mountable so I need to make a mini break out for it.
- The compact flash interface is mounted but needs to be wire wrapped to the remaining available pins on the CPLD.