tech details of how DragonIP is connected to Apple BUS?

Tech support questions for the Uther board may be posted here. You may want to read the FAQ first as you may find what your looking for there first.

Moderator: support

tech details of how DragonIP is connected to Apple BUS?

Postby aiiadict » Sun Jun 12, 2005 6:33 pm


Can you publish some technical details on your Uther card? I'd like to know which signals on the Apple BUS are connected to the card, and which ones are used during operation.

Also, DragonIP command list, protocol, register reading, and data send/receive description would be nice.

Goal: get someone to emulate Uther card for AppleWin

Posts: 33
Joined: Mon May 16, 2005 9:44 pm
Location: california

Uther details

Postby support » Sun Jun 12, 2005 9:17 pm

Uther uses the IPDragon module

Data sheet:

The module has a Cirrus cs8900a chip on it.

Product info and Data Sheets:

If you look at the signals that the Dragon requires you will see Data bus D0-D7. This is gated through a 74LS245. The Apple II R/W signals are split by the use of a 2 to 4 decoder 74LS139 to generate RD and WR respectivly.

DEVSEL is used for chip enable and IP Dragon CS

A 74LS00 inverter is used to invert the RESET signal.

You have 4 address lines A0-A3 that give you access to the 16 addressable registers.

INT is not used.

+5 volts and GND are supplied from the Apple II bus.


I believe the VICE emulator already ready has cs8900a emulation so it could be ported to Applewin or kegs.

Site Admin
Posts: 169
Joined: Tue Mar 08, 2005 10:49 pm
Location: Ajax, On, Canada

Return to Tech Support

Who is online

Users browsing this forum: No registered users and 1 guest